|
VL |
Sine Wave |
100MHz |
14.0 x 9.0 |
|
Low Phase Noise
Small SMD Package
Low Power Consumption |
|
|
VW CMOS |
CMOS |
1.5~170MHz |
5.0 x 3.2 |
|
Smaller Size
Good Linearity |
|
|
VW LVPECL / LVDS |
LVPECL / LVDS |
20~200MHz |
5.0 x 3.2 |
|
Smaller Size
Good Linearity
Differential Logic |
|
|
VT CMOS |
CMOS |
1.5~200MHz |
7.0 x 5.0 |
|
Tight Symmetry
Low Jitter |
|
|
VT-M CMOS |
CMOS |
60~200MHz |
7.0 x 5.0 |
|
Tight Symmetry |
|
|
VT LVPECL / LVDS |
LVPECL / LVDS |
1.5~200MHz |
7.0 x 5.0 |
|
Tight Symmetry
Wide Pulling Range
Low Jitter
Differential Logic |
|
|
VT-M LVPECL |
LVPECL |
100~800MHz |
7.0 x 5.0 |
|
Tight Symmetry
Wide Pulling Range
Differential Logic
Up To 800 MHz |
|
|
VK |
LVPECL / LVDS |
1.5~200MHz |
14.2 x 9.3 |
|
Metal Cover, FR-4 PCB Based SMD package
Differential Logic
Up to 200 MHz |
|