| 产品图片 | 型号 | 类型 | 频率 | 尺寸 | 注释 | 反馈 | |
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VW CMOS | CMOS | 1.5~170MHz | 5.0 x 3.2 |  |
Smaller Size Good Linearity |  |
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VW LVPECL / LVDS | LVPECL / LVDS | 20~200MHz | 5.0 x 3.2 | |
Smaller Size Good Linearity Differential Logic | |
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VT CMOS | CMOS | 1.5~200MHz | 7.0 x 5.0 | |
Tight Symmetry Low Jitter | |
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VT-M CMOS | CMOS | 60~200MHz | 7.0 x 5.0 | |
Tight Symmetry | |
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VT LVPECL / LVDS | LVPECL / LVDS | 1.5~200MHz | 7.0 x 5.0 | |
Tight Symmetry Wide Pulling Range Low Jitter Differential Logic | |
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VT-M LVPECL | LVPECL | 100~800MHz | 7.0 x 5.0 | |
Tight Symmetry Wide Pulling Range Differential Logic Up To 800 MHz | |
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VK | LVPECL / LVDS | 1.5~200MHz | 14.2 x 9.3 | |
Metal Cover, FR-4 PCB Based SMD package Differential Logic Up to 200 MHz | |
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T9 | CMOS / Clipped Sine Wave | 10~40MHz | 20.4 x 12.8 | |
High Precision For -40°C~+105°C, ±100ppb -40°C~+85°C, ±50ppb | |
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TW | CMOS / Clipped Sine Wave | 10~40MHz | 5.0 x 3.2 | |
High Precision For -10°C~+ 70°C, ± 0.05 ppm -40°C~+ 85°C, ± 0.2 ppm | |
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TT | CMOS / Clipped Sine Wave | 5~52MHz | 7.0 x 5.0 | |
High Precision For -40°C ~+85°C, ± 0.2 ppm | |
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TT Stratum3 | CMOS / Clipped Sine Wave | 5~52MHz | 7.0 x 5.0 | |
Overall ± 4.6ppm Including 20 Years Aging (@ -40°C~+ 85°C) | |
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TS | CMOS / Clipped Sine Wave | 5~40MHz | 7.0 x 5.0 | |
High Precision For -40°C ~+85°C, ± 0.28 ppm | |
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